Boundary scan is a structured test technique that was developed to test IC (integrated circuit) interconnects on PWBs (printed wire boards) when physical access is impossible, difficult, or impractical. Implementation of the boundary scan test technique requires that a shift register and latch be placed at the functional I/Os of an IC. Each I/O pin can be driven to a known state or the current logic level can be captured and scanned out via a four-wire serial bus. The test bus and protocol as well as the behavior of the boundary cells are defined in IEEE Std. 1149.1. This standard defines a standard test logic architecture for implementing boundary scan functions which can be included in an integrated circuit for the purpose of testing the interconnects to the integrated circuit, the integrated circuit itself, or other integrated circuits. The test architecture is defined to include a test access port (TAP) having connections for a test clock pin (TCK), a test mode select pin (TMS), a test data input pin (TDI) and a test data output pin (TDO). The test architecture also includes a TAP controller (boundary-scan state machine), all as shown in FIG. 1. Thus, as IC pin counts increase, pin spacing decreases, and pin accessibility disappears, boundary scan (B-S) is playing an increasing role in design verification, manufacturing, and the testing of new products.
At present boundary-scan (B-S) allows all pins of a B-S chip to be controlled uniformly by either system or B-S logic. The requirement that all pins are controlled by the same logic (that is, for the same chip, some pins cannot be controlled by system logic while others are controlled by B-S registers), however, limits B-S usage for many applications, for example, those applications requiring fault injection.
Recently, several references have demonstrated methods of using B-S for fault injection. For example, designs have been proposed by Chau, Savio in "Fault Injection Boundary Scan Design for Verification of Fault Tolerant Systems", Proc. of International Test Conference, October, 1994, pp. 677-681 to modify B-S circuitry to inject faults at individual pins, in which the value of the B-S register is used to determine if a fault is injected or not. In a first design, the faulty values to be injected must be identical which is a drawback in itself. In a second design, faulty values are the contents of a shift (capture) portion of the B-S register. There are two drawbacks in this design--first, when shifting faulty values into to the B-S register, the value of the output pins may be rippling, and second, when an update state is entered, the fault injection selection pattern, which is kept in the update portion of the B-S register, may be corrupted. In another reference, Nadeau-Dostie, B. et al., "A new hardware fault insertion scheme for system diagnostics verification", Proc. of International Test Conference, October, 1995, pp. 994-1002, an alternate fault injection method is proposed for system diagnostics verification. It achieves several improvements over the designs in Chau, but the area overhead can be as high as 50 to 100% depending on the pad type. There are also some compliance issues with the IEEE 1149.1 standard.
Accordingly, in order to improve fault generation techniques, and to simplify test generation for inter-chip path delay testing, a need exists to provide for mixed control of pins in boundary scan applications.